- 目錄
第1篇 ic數(shù)字工程師崗位職責(zé)
數(shù)字ic工程師 泰斗微電子科技有限公司 泰斗微電子科技有限公司,泰斗微電子 1.根據(jù)項(xiàng)目要求完成芯片系統(tǒng)或模塊的詳細(xì)設(shè)計(jì)文檔撰寫(xiě);
2.負(fù)責(zé)rtl實(shí)現(xiàn)及仿真驗(yàn)證工作;
3.協(xié)助后端相關(guān)工作;
4.協(xié)助測(cè)試進(jìn)行問(wèn)題分析
5.編寫(xiě)相關(guān)技術(shù)文檔;
6.保證任務(wù)按時(shí)有效完成;
7.按時(shí)合理向部門(mén)經(jīng)理以及項(xiàng)目經(jīng)理匯報(bào)工作情況;
要求:
1.通信、電子類(lèi)相關(guān)專(zhuān)業(yè),2年以上ic設(shè)計(jì)經(jīng)驗(yàn)
2.精通verilog,hdl代碼編寫(xiě)及驗(yàn)證
3.熟練使用modelsim/ise/quarter/nc-verilog/vcs等eda工具
4.熟練掌握數(shù)字電路設(shè)計(jì)流程及方法
5.具備數(shù)字信號(hào)處理相關(guān)知識(shí)背景
第2篇 asic數(shù)字電路設(shè)計(jì)工程師崗位職責(zé)
asic design engineer 數(shù)字電路設(shè)計(jì)工程師 北京百瑞互聯(lián)技術(shù)有限公司 北京百瑞互聯(lián)技術(shù)有限公司,百瑞 job description
? independent block and soc rtl design and verification
? analog and digital ip integration
? rtl handoff quality check using eda tools
? prepare signoff quality full chip sdc file
? prepare signoff quality full chip upf file
? support asic implementation
? support fpga prototyping
? support dft integration
? support software and system production
? write design documents
qualifications
? 2+ years hands-on experience in asic rtl design. experience in bluetooth, mobile computing or iot is a plus
? familiar with popular asic solutions (including specification and architecture)
? familiar with asic design verification and implementation flow
? familiar with relevant qa tools (for example spyglass)
? strong debugging and analytical skills, generate ideas, and provide innovative solutions to solve technical problems
? english documents reading
? good programming in perl/python, tcl and shell programming
? self-motivated, team work, and good communication skills
第3篇 ic數(shù)字邏輯設(shè)計(jì)工程師崗位職責(zé)
職位描述:崗位要求:1、電子、信息、通信、應(yīng)用數(shù)學(xué)、應(yīng)用物理等相關(guān)專(zhuān)業(yè)畢業(yè),全日制本科或以上學(xué)歷。2、有一年邏輯設(shè)計(jì)電路設(shè)計(jì)或驗(yàn)證經(jīng)驗(yàn)。3、有良好電路基礎(chǔ)知識(shí)和...
第4篇 asic數(shù)字電路工程師崗位職責(zé)
asic verification engineer 數(shù)字電路驗(yàn)證工程師 北京百瑞互聯(lián)技術(shù)有限公司 北京百瑞互聯(lián)技術(shù)有限公司,百瑞 job description
? independent soc verification
? responsible for golden models and micro-architecture using uvm
? upf based low power verification
? post simulation and functional pattern generation for testing
? support asic implementation
? support fpga prototyping
? support software and system productions
? write verification plan documents
qualifications
? 2+ years hands-on experience in asic rtl design. experience in bluetooth, mobile computing or iot is a plus
? familiar with uvm verification
? experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies
? experience in crafting testbench environments for block and system level verification
? strong debugging and analytical skills
? asic design verification and implementation flow knowledge
? good knowledge to upf and low power verification (for example vclp, verdipa and vcs-nlp)
? english documents reading
? good programming in perl/python, tcl and shell programming
? good team work and communication skills
第5篇 ic數(shù)字設(shè)計(jì)工程師崗位職責(zé)
數(shù)字ic設(shè)計(jì)工程師 紫光同芯微電子有限公司 紫光同芯微電子有限公司,同方微電子,紫光同芯 數(shù)字ic設(shè)計(jì)工程師
工作內(nèi)容:
1、根據(jù)需求分析文檔,設(shè)計(jì)系統(tǒng)整體框架
2、完成模塊級(jí)設(shè)計(jì)文檔
3、根據(jù)設(shè)計(jì)文檔,確保設(shè)計(jì)的良好實(shí)現(xiàn)
4、確定驗(yàn)證方案,完成模塊級(jí)驗(yàn)證和系統(tǒng)級(jí)驗(yàn)證
5、根據(jù)評(píng)測(cè)方案,完成芯片評(píng)測(cè),定位并解決評(píng)測(cè)問(wèn)題
任職資格:
1、電子、微電子相關(guān)專(zhuān)業(yè)本科以上學(xué)歷
2、熟悉數(shù)字邏輯設(shè)計(jì),熟練掌握verilog語(yǔ)言,熟悉ic設(shè)計(jì)開(kāi)發(fā)流程
3、熟悉arm體系架構(gòu)和amba總線,具備soc設(shè)計(jì)經(jīng)驗(yàn);熟練使用synopsys開(kāi)發(fā)工具
4、掌握數(shù)字電路結(jié)構(gòu)的功能和特性,有較強(qiáng)的理論分析和動(dòng)手能力
